128 Bit, Exascale Memory Reference Models for Next Generation, ExaByte Capacity Physical Memory Systems
Time:
Tuesday, June 20, 2017 09:30 am - 09:45 am
Room:
Panorama 1 Messe Frankfurt
Breaks:
07:30 am - 10:00 am Welcome Coffee
Speaker:
Steve Wallach, Micron
Abstract:
As we plan for EXASCALE computing in the next decade, we must also plan for the mechanisms needed to reference ExaBytes of Physical Memory. These mechanisms may require having an address space greater than 64 bits. We will examine architectural defined memory reference extensions that include: 128 bit virtual address, global protection control, incorporation of non-volatile memory in the processor address hierarchy and PGAS memory reference mechanisms.
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