JUNE 18–22, 2017
FRANKFURT AM MAIN, GERMANY

Session Details
 
Name: Performance Engineering for HPC: Implementation, Processes & Case Studies
 
Time: Thursday, June 22, 2017
09:00 am - 06:00 pm
 
Room:   Gold 3  
 
Breaks:11:00 am - 11:30 am Coffee Break
01:00 pm - 02:00 pm Lunch
04:00 pm - 04:30 pm Coffee Break
 
Organizer:   Georg Hager, RRZE
  Matthias Müller, RWTH Aachen University
  Gerhard Wellein, RRZE & University of Erlangen-Nuremberg
 
Speaker:   Christian Bischof, University of Darmstadt
  Jan Eitzinger, RRZE
  Robert Henschel, Indiana University
  Torsten Hoefler, ETH Zurich
  Jens Jägersküpper, German Aerospace Center (DLR)
  Harald Köstler, University of Erlangen-Nuremberg
  Jesús Labarta, BSC
  Dirk Pleiter, JSC
  Cyrus Proctor, TACC
  Alexander Reinefeld, ZIB & Humboldt-University Berlin
 
Abstract:   The days of mystic "black-box" performance engineering (PE) of computer programs are gone. Modern tools have entered the scene, endowing developers with an unprecedented level of analysis of code performance. However, as we face more and more complex system architectures, HPC experts have an even more vital role to play when it comes to code optimization and parallelization. Making sense of performance data and taking the right action for the problem at hand are still daunting tasks. Automatic frameworks may provide local solutions but do not deliver deeper insight for long-term performance-aware code development in a universe of increasing hardware diversity and code intricacy. Consequently, computing centers and HPC developer communities provide human assistance to support end users at various levels of sophistication. This workshop gives an overview of PE activities at computing centers and CSE research communities, highlighting structured, process-oriented approaches. The presentations span a range of topics, from structural issues in providing the right level of service to application programmers conducting actual performance optimizations. The workshop will thus be of wide interest to decision makers, HPC experts, tool developers, and programmers alike. 

Targeted Audience
HPC professionals, academics, and students who want to get a thorough overview of performance modeling techniques presented by experts in the field. Due to the large diversity among speakers we expect many different views on the subject and, correspondingly, lively discussions. 

For more details, please visit the workshop webpage at https://blogs.fau.de/hager/bofs/isc17-workshop