Presentation
Many-core Computing on Intel Processors: Applications, Performance and Best-Practice Solutions
Workshop Organizers
Speakers
Event Type
Workshop
AI/Machine Learning/Deep Learning
Parallel Algorithms
Parallel Applications
Performance Analysis and Optimization
Programming Models & Languages
TimeThursday, June 28th9am - 6pm
LocationMatrix
DescriptionThe workshop will bring together software developers and technology experts to share challenges, experiences and best‐practice methods for the optimization of HPC, Machine Learning (ML) and Data Analytics (DA) workloads on Intel Xeon Scalable Processors and Intel Xeon Phi Processors. The workshop will cover application performance and scalability challenges at all levels – from intra-node performance up to large-scale compute systems.
The keynote will introduce the main features of current-generation Intel processors models for HPC and ML/DA workloads - including the various memory configurations and modes of operation available - and provide a refresher on what’s public about future processor generations.
The submitted talks cover optimization and scalability topics in real-world HPC and ML applications, e.g. data layouts and code restructuring for efficient SIMD operation, utilization of new AVX-512 instructions, work distribution and thread management. Furthermore, aspects related to deeper memory hierarchies (High-Bandwidth Memory, node-local persistent storage) are of particular interest. The usability of tools for development, debugging and performance analysis will be covered.
The panel session provides an opportunity to discuss optimization strategies for Intel many-core processors including Intel Xeon SP series, “Knights Landing” (KNL), and “Knights Mill” (KNM), and to provide feedback to the toolchain developers.
The keynote will introduce the main features of current-generation Intel processors models for HPC and ML/DA workloads - including the various memory configurations and modes of operation available - and provide a refresher on what’s public about future processor generations.
The submitted talks cover optimization and scalability topics in real-world HPC and ML applications, e.g. data layouts and code restructuring for efficient SIMD operation, utilization of new AVX-512 instructions, work distribution and thread management. Furthermore, aspects related to deeper memory hierarchies (High-Bandwidth Memory, node-local persistent storage) are of particular interest. The usability of tools for development, debugging and performance analysis will be covered.
The panel session provides an opportunity to discuss optimization strategies for Intel many-core processors including Intel Xeon SP series, “Knights Landing” (KNL), and “Knights Mill” (KNM), and to provide feedback to the toolchain developers.
Links
Workshop Organizers
Speakers
Research Scientist
Scientific Associate
Applications Consultant