Presentation
(RP23) A Skewed Multi-Bank Cache for Vector Processors
SessionResearch Posters Session
Event Type
Research Poster
Computer Architecture
TimeTuesday, June 18th8:30am - 10am
LocationSubstanz 1, 2
DescriptionVector supercomputers are widely used in scientific and engineering applications that require a high memory bandwidth. Recently, the key component of the vector supercomputers, a vector processor, has adopted a multi-core architecture that plays an important role for improving computing performance. On the other hand, improvement of the memory bandwidth is limited due to memory technology trends. Hence, the vector processor employs multi-bank cache memories in order to obtain high memory data transfer capability. It is expected that these trends continue, and more cores and caches with more banks will be used even in future vector processors. However, cache configurations suitable for vector processors are not clear in the case of many cores and many cache banks. The preliminary evaluation using a simulator shows that a vector processor with many cores and many banks causes a lot of conflict misses in the stencil kernel. Therefore, this poster proposes a skewed multi-bank cache for the many-core vector processors that enables to suppress conflict misses with a low associativity. This poster examines odd-multiplier displacement hashing as a hash function for skewing and SRRIP as a cache replacement policy. The evaluation results show that, by adopting the skewed multi-bank cache for a many-core vector processor, almost ideal hit ratio can be obtained in the stencil kernel.
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