The Message Passing Interface (MPI) has been the de facto standard for parallel programming for nearly two decades now. However, a vast majority of applications only rely on basic MPI-1 features without taking advantage of the rich set of functionality the rest of the standard provides. Further, with the advent of MPI-3 (released in September 2012), a vast number of new features have been introduced in MPI, including efficient one-sided communication, support for external tools, non-blocking collective operations, and improved support for topology-aware data movement. The upcoming MPI- 4 standard aims at introducing further improvements to the standard in a number of aspects. This is an advanced-level tutorial that will provide an overview of various powerful features in MPI, especially with MPI-2 and MPI-3, and will present a brief preview into what is being planned for MPI-4.

The computational science and engineering (CSE) community is in the midst of an extremely challenging period created by the confluence of disruptive changes in computing architectures, demand for greater scientific reproducibility, and new opportunities for greatly improved simulation capabilities, especially through coupling physics and scales. Computer architecture changes require new software design and implementation strategies, including significant refactoring of existing code. Reproducibility demands require more rigor across the entire software endeavor. Code coupling requires aggregate team interactions including integration of software processes and practices. These challenges demand large investments in scientific software development and improved practices. Focusing on improved developer productivity and software sustainability is both urgent and essential.

This tutorial will provide information and hands-on experience with software practices, processes, and tools explicitly tailored for CSE. Goals are improving the productivity of those who develop CSE software and increasing the sustainability of software artifacts. We discuss practices that are relevant for projects of all sizes, with emphasis on small teams, and on aggregate teams composed of small teams. Topics include software licensing, effective models, tools, and processes for small teams (including agile workflow management), reproducibility, and scientific software testing (including automated testing and continuous integration).

Large-scale numerical simulations, observations and experiments are generating very large datasets that are difficult to analyze, store and transfer. Data compression is an attractive and efficient technique to significantly reduce the size of scientific datasets. This tutorial reviews the state of the art in lossy compression of scientific datasets covering the most effective decorrelation, approximation and coding techniques. It details the two leading compressors (SZ and ZFP) that offer lossless and lossy compressions.It also introduces compression error assessment metrics and the Z-checker tool to analyze the difference between initial and decompressed datasets. The tutorial offers hands-on exercises using SZ and ZFP as well as Z-checker. It addresses the following questions: Why compression? How does compression work? How to measure and control compression error of lossy compressors? The tutorial uses examples of real-world compressors and scientific/engineering datasets to illustrate the different compression techniques and their performance. The tutorial is given by two of the leading teams in this domain and targets primarily beginners interested in learning about lossy compression for scientific data. This half-day tutorial is improved from the evaluations of the highly rated tutorials given on this topic at ISC17, SC17, SC18, ISC19, SC19.

HPC application developers encounter significant challenges getting their codes to run correctly on leadership computer systems consisting of large numbers of interconnected multi-socket multicore processor nodes often with attached accelerator devices. They also need effective tools and methods to track and assess their codes’ execution performance as they aim to get ready for production on current or prospective exascale computer systems.

This tutorial presents the methodology developed and applied over several years within the EU HPC Centre of Excellence Performance Optimisation and Productivity (POP). Its focus is the hierarchy of execution efficiency and scaling metrics that identify the most critical issues and quantify potential benefits of remedies. The metrics can be readily compared and determined by a variety of tools for applications in any language employing standard MPI, OpenMP and other multi-threading and offload paradigms. Widely-deployed open-source tools will be used to demonstrate this process with provided performance measurements of actual HPC application executions (ranging from CFD to neuroscience), allowing tutorial participants to repeat this on their own computers and preparing them to locate and diagnose efficiency and scalability issues in their own parallel application codes.

Within just the past few years, the use of containers has revolutionized the way in which industries and enterprises have developed and deployed computational software and distributed systems. The containerization model has gained traction within the HPC community as well with the promise of improved reliability, reproducibility, portability, and levels of customization that were previously not possible on supercomputers. This adoption has been enabled by a number of HPC-compatible Container runtimes that have emerged including Singularity, Shifter, Enroot, Charliecloud, Podman and others.

This hands-on tutorial looks to train users on the usability of containers on HPC resources. We will provide background on Linux containers, along with introductory hands-on experience building a container image, sharing the container and running it on a HPC cluster. Furthermore, the tutorial will provide more advanced information on how to run MPI-based and GPU-enabled HPC applications, as well as on advanced build methods and best practices. Cutting-edge examples will include bioinformatics and fluid dynamics. Users will leave the tutorial with a solid foundational understanding of how to utilize containers with HPC resources through Shifter, Singularity and Podman, as well as an in-depth knowledge to deploy custom containers on their own resources.

This tutorial presents state-of-the-art performance tools for leading-edge HPC systems founded on the community-developed Score-P instrumentation and measurement infrastructure, demonstrating how they can be used for performance engineering of effective scientific applications based on standard MPI, OpenMP, hybrid combination of both, and increasingly common usage of accelerators. Parallel performance tools from the Virtual Institute - High Productivity Supercomputing (VI-HPS) are introduced and featured in hands-on exercises with Score-P, Scalasca, Vampir, and TAU. We present the complete workflow of performance engineering, including instrumentation, measurement (profiling and tracing, timing and PAPI hardware counters), data storage, analysis, tuning, and visualization. Emphasis is placed on how tools are used in combination for identifying performance problems and investigating optimization alternatives. Using their own notebook computers with a provided E4S [https://e4s.io] OVA image containing all of the necessary tools (running within a virtual machine), participants will conduct exercises on a contemporary HPC system where remote access will be provided for the hands-on sessions through AWS running the E4S image. This will help to prepare participants to locate and diagnose performance bottlenecks in their own parallel programs.

The recent advances in Deep Learning (DL) have led to many exciting challenges and opportunities for CS and AI researchers alike. Modern DL frameworks like TensorFlow, PyTorch, and several others have emerged that offer ease of use and flexibility to train, and deploy Deep Neural Networks (DNNs). In this tutorial, we will provide an overview of interesting trends in DNN design and how cutting-edge hardware architectures and high-performance interconnects are playing a key role in moving the field forward. We will also present an overview of different DNN architectures and DL frameworks. Most DL frameworks started with a single-node design. However, approaches to parallelize the process of DNN training are also being actively explored. The DL community has moved along different distributed training designs that exploit communication runtimes like MPI and NCCL. We highlight new challenges and opportunities for communication runtimes to exploit high-performance CPU and GPU architectures to efficiently support large-scale distributed DNN training. We also highlight some of our co-design efforts to utilize MPI for large-scale DNN training on cutting-edge CPU and GPU architectures. Finally, we include hands-on exercises to enable the attendees to gain first-hand experience of running distributed DNN training experiments on a modern GPU cluster.

The trend over the past decade towards increasingly diverse heterogeneous hardware has had a profound impact on the landscape of programming models and execution models. Single-source heterogeneous programming models for performance portability have particularly gained popularity in the past few years due to the increasingly insurmountable plethora of vendor-specific interfaces for heterogeneous hardware. With more than a decade of experience in the field, Kokkos has emerged as a leader in the area of performance-portable parallel programming models, with more than a hundred projects utilizing the latest in CPU and GPU hardware through its generic interface. This tutorial, given in various forms and venues around the globe, presents a practical introduction to the Kokkos programming model. Many iterations on the tutorial material have shown that most attendees acquire the necessary skills to begin porting production applications to the Kokkos programming model after just one day of instruction. Interactive practice exercises teach not only the fundamental syntax and semantics of the programming model, but also the performance characteristics of parallel applications on modern heterogeneous hardware. Presentations of the Kokkos Kernels and Tooling libraries are also included, leaving attendees with all of the necessary skills to use Kokkos in their own HPC applications.

The modern scientific software stack includes thousands of packages, from C, C++, and Fortran libraries, to packages written in interpreted languages like Python and R. HPC applications may depend on hundreds of packages spanning all of these ecosytems. To achieve high performance, they must also leverage low- level and difficult-to-build libraries such as MPI, BLAS, and LAPACK. Integrating this stack is extremely challenging. The complexity can be an obstacle to deployment at HPC sites and deters developers from building on each others’ work. Spack is an open source tool for HPC package management that simplifies building, installing, customizing, and sharing HPC software stacks. In the past few years, its adoption has grown rapidly: by end-users, by HPC developers, and by the world’s largest HPC centers. Spack provides a powerful and flexible dependency model, a simple Python syntax for writing package build recipes, and a repository of over 3,800 community-maintained packages. This tutorial provides a thorough introduction to Spack’s capabilities: installing and authoring packages, integrating Spack with development workflows, and using Spack for deployment at HPC facilities. Attendees will leave with foundational skills for using Spack to automate day-to-day tasks, along with deeper knowledge for applying Spack to advanced use cases.

With the increasing prevalence of multi-core processors, shared-memory programming models are essential. OpenMP is a popular, portable, widely supported and easy-to-use shared-memory model. Since version 3.0 released in 2008, OpenMP offers tasking to support the creation of composable parallel software blocks and the parallelization of irregular algorithms. Developers usually find OpenMP easy to learn. However, mastering the tasking concept of OpenMP requires a change in the way developers reason about the structure of their code and how to expose the parallelism of it. Our tutorial addresses this critical aspect by examining the tasking concept in detail and presenting patterns as solutions to many common problems.

We assume attendees understand basic parallelization concepts and know the fundamentals of OpenMP.We present the OpenMP tasking language features in detail and focus on performance aspects, such as introducing cut-off mechanisms, exploiting task dependencies and preserving locality. All aspects are accompanied by extensive case studies. Throughout all topics, we present the recent additions of the OpenMP 5.0 major release from 2018.

The Scalable Vector Extension (SVE) is the next-generation SIMD instruction set for Armv8-A. SVE does not specify a vector length and it uses predicates to dynamically select vector lanes. For many developers, this presents an entirely new way of thinking about vectorization. This tutorial will introduce tools from the Arm community for SVE programming and performance analysis, i.e. compilers, scientific libraries, profilers, and debuggers. The content of this tutorial will be notably different from past SVE tutorials as this will be the first time a public SVE tutorial will be taught on SVE hardware. We plan to provide remote access to SVE-enabled CPUs for this tutorial. Hands-on exercises will explore the unique features of SVE and demonstrate their applicability to a range of common programing motifs. This tutorial will demonstrate how to capture high-utility information and present it in meaningful ways, i.e. how much time is spent in application routines, where these routines are called in the source code, and how well the routines vectorize. Attendees will complete the tutorial with a working understanding of SVE and knowledge of how SVE may be used in their applications.

SYCL is a programming model that lets developers write parallel applications for a wide variety of devices (CPUs, GPUs, FPGAs and more) from a single code base using standard C++. Given the growing heterogeneity of processor roadmaps, moving to a platform-independent model such as SYCL is essential for modern software developers. SYCL has the further advantage of supporting a single-source style of programming from completely standard C++. In this tutorial, we will introduce SYCL and provide programmers with a solid foundation they can build on to gain mastery of this language. The real value in SYCL comes from its use in writing applications. We will explore how SYCL can be used to write serious applications, covering intermediate to advanced features of SYCL as well as some of the tools and libraries that support SYCL application development. This is a hands-on tutorial. Students will be given exercises that represent key design patterns encountered by people who program heterogeneous systems.

Morning: A Hands-On Introduction to SYCL Afternoon: Application Development with SYCL

InfiniBand (IB), High-speed Ethernet (HSE), RoCE, Omni-Path, EFA, and Slingshot technologies are generating a lot of excitement towards building next generation High-End Computing (HEC) systems including clusters, datacenters, file systems, storage, cloud computing and Big Data (Hadoop, Spark, HBase and Memcached) environments. This tutorial will provide an overview of these emerging technologies, their offered architectural features, their current market standing, and their suitability for designing HEC systems. It will start with a brief overview of IB, HSE, RoCE, Omni-Path, EFA, Slingshot, and Omni-Path. In-depth overview of the architectural features of IB, HSE (including iWARP and RoCE), and Omni-Path, their similarities and differences, and the associated protocols will be presented. An overview of the emerging NVLink, NVLink2, and NVSwitch architectures will also be given. Next, an overview of the OpenFabrics stack which encapsulates IB, HSE, and RoCE (v1/v2) in a unified manner will be presented. An overview of libfabrics stack will also be provided. Hardware/software solutions and the market trends behind these networking technologies will be highlighted. Sample performance numbers of these technologies and protocols for different environments will be presented. Finally, hands-on exercises will be carried out for the attendees to gain first-hand experience of running experiments with high-performance networks.

In this introductory tutorial, you will learn what "high performance computing" means and what differentiates it from more mainstream areas of computing. You will also be introduced to the major applications that use high performance computing for research and commercial purposes, and how AI and HPC interact with each other. Then, we present the major HPC system architectures needed to run these applications. Finally, you will be provided with an overview of the languages and paradigms used to program HPC applications and systems. The tutorial will be presented by Dr.-Ing. Bernd Mohr from the Jülich Supercomputing Centre.

Contents • HPC Application Areas • Interplay between AI and HPC • Basic Terminology • Evaluating Program Performance • HPC Hardware Architectures ◦ Shared Memory System ◦ Distributed Memory Systems ◦ Hybrid Systems ◦ Accelerators • Parallel Programming ◦ Basics of Parallel Programming ◦ Inter-node Parallel Programming (MPI) ◦ Intra-node Parallel Programming (OpenMP) ◦ Accelerator Programming (OpenMP5, OpenACC, CUDA, HIP)

Installing scientific software for supercomputers is known to be a tedious and time-consuming task. Increasing HPC user community diversity, as well as hardware complexity, continues to deepen the application software stack. Delivering optimised software installations and providing access to these installations in a reliable, user-friendly way is a highly non-trivial task that affects the application developer, the HPC user support teams, and the users themselves. This tutorial addresses this issue, providing the attendees with the knowledge to install and manage software in a clean and reproducible way. For this, the tutorial introduces EasyBuild, a software build and installation framework implemented in Python. It supports implementing (complex) installation procedures concisely, and is able to fully autonomously perform optimised software installations. It is open source and has a thriving community, and supports more than 2,200 (scientific) software packages. It is well integrated with different implementations of environment modules (Lmod, Tcl, C) to generate module files automatically and present them in a consistent way.

This tutorial will expose the audience to the rapidly expanding landscape of mixed- and multi-precision methods. The ongoing cross-pollination between high-performance computing (HPC) and machine learning (ML) is leading to intelligent computational steering of large-scale simulations. More importantly for this tutorial, sharing of the hardware platforms and exploiting their wide range of computational modes has led to proliferation of multiple representations of floating-point data—and increased interest in new methods that exploit them. Against the backdrop of high-performance libraries produced by internet-scale companies, hardware vendors, national laboratories, and academic institutions, we will show the recent algorithmic progress in exploiting multiple precisions for increased efficiency in performance, communication, and/or storage. The techniques presented in the tutorial employ floating-point representations such as limited precision, quantized integers, and modular precision ecosystems. A portion of this tutorial will cover the fundamentals of the HPC software development in order to introduce the audience to some of the low-level details of coding for multiple precisions on modern hardware, including accelerators. The hardware focus of the tutorial will feature floating-point representation and performance of the recent supercomputing and industrial computing CPUs and accelerators, as well as less mainstream devices meant for more specific tasks at limited power envelopes.

As HPC continues to move towards a model of multicore and accelerator programming, a detailed understanding of shared-memory models and how best to use accelerators has never been more important. OpenMP is the de facto standard for writing multithreaded code to take advantage of shared memory platforms, but to make optimal use of it can be incredibly complex.

With a specification running to over 500 pages, OpenMP has grown into an intimidating API viewed by many as for “experts only”. This tutorial will focus on the 16 most widely used constructs that make up the ‘OpenMP common core’. We will present a unique, productivity-oriented approach by introducing its usage based on common motifs in scientific code, and how each one will be parallelized. This will enable attendees to focus on the parallelization of components and how components combine in real applications.

Attendees will use active learning through a carefully selected set of exercises, building knowledge on parallelization of key motifs (e.g. matrix multiplication, map reduce) that are valid across multiple scientific codes in everything from CFD to Molecular Simulation.

Attendees will need to bring their own laptop with an OpenMP compiler installed (more information at www.openmp.org).

Energy efficiency has become a first class citizen in the design of large computing systems. While GPUs and custom processors show merit in this regard, reconfigurable architectures, such as FPGAs, promise another major improvement in energy efficiency, constituting a middle ground between fixed hardware architectures and custom-built ASICs. This tutorial shows how high-level synthesis (HLS) can be harnessed to productively achieve scalable pipeline parallelism on FPGAs. Attendees will learn how to target FPGA resources from high-level C++ or OpenCL code, guiding the mapping from imperative code to hardware, enabling them to develop massively parallel designs. We treat well-known examples from the software world, relating traditional code optimizations to hardware, building on existing knowledge when introducing new topics. By bridging the gap between software and hardware optimization, our tutorial aims to enable developers from a large set of backgrounds to start tapping into the potential of FPGAs for high performance codes.

Containers and virtualization technologies constitute key enabling factors for flexible resource management in modern data centers, and particularly in cloud environments. HPC operators and cloud providers need to manage complex infrastructures in a seamless fashion to support the highly dynamic and heterogeneous workloads and hosted applications customers deploy. Various virtualization-containerization technologies contribute to the overall picture in different ways: machine virtualization, with its capability to enable consolidation of multiple under­utilized servers with heterogeneous software and operating systems (OSes), and its capability to live­-migrate a fully operating virtual machine (VM) with a very short downtime, enables novel and dynamic ways to manage physical servers; OS-­level virtualization (i.e., containerization), with its capability to isolate multiple user­-space environments and to allow for their co­existence within the same OS kernel, promises to provide many of the advantages of machine virtualization with high levels of responsiveness and performance; lastly, unikernels provide for many virtualization benefits with a minimized OS/library surface. The Workshop on Virtualization in High­-Performance Cloud Computing (VHPC) aims to bring together researchers and industrial practitioners facing the challenges posed by virtualization, containerization, and orchestration techniques for deploying HPC and HPC-like applications in large data centers.

Live-Stream: https://us02web.zoom.us/webinar/register/WN_vC5pwmgbQ6ypJEfyQ8nHIg

This workshop aims to provide insight into the current state and trends in Monitoring and Operational Data Analytics (MODA), to identify potential gaps, and to offer an outlook into the future of MODA at a large scale together with possible solutions for the upcoming Exascale systems. The focus of the MODA21 workshop will be on currently envisioned solutions and best practices for monitoring systems at data centers and HPC sites, as well as on effective strategies for analyzing and interpreting the collected operational data. The workshop is unique to the European HPC arena in addressing these topics. We envision a balanced mix between a keynote address, peer-reviewed technical paper presentations, invited talks, and a panel discussion.

Recent years have seen a surge of investment in AI chip companies worldwide. These companies are however mostly targeting applications outside of the scientific computing community. As the use of ML accelerates in the HPC field itself, there is concern that the scientific community should influence the design of this new specialized hardware. Indeed, scientific computing has a distinctive set of requirements regarding workload type, usage model, and platform administration. How those chips answer those demands will shape the future of their integration within the global scientific computing infrastructure. In this workshop, we propose to let the community and select vendors engage on questions related to the low-level aspects of this new hardware and its integration with HPC systems, as well as to the software APIs and compiler toolchains that will be available. This proposal follows the outcome of a successful ISC20 workshop where an emphasis on compiler technology emerged. In this iteration, we will push the agenda further by discussing existing efforts to leverage ML hardware for scientific HPC applications.

The ever increasing scale of today’s HPC simulations with their inherent I/O bottleneck makes in situ an essential approach for data analysis. Nowadays, the rate of data generation easily exceeds available bandwidth or storage capabilities significantly. Consequently, analysis and visualization has to be coubled in situ to a live simulation in order to facilitate comprehensive investigation. In doing so, data abstracts are generated that capture much more information than otherwise possible.

The “International Workshop on In Situ Visualization” provides a venue for speakers to share practical expertise and experience with in situ visualization approaches. We encourage contributed talks on methods and workflows that have been applied in this field. Speakers should detail if and how the application drove abstractions or other kinds of data reductions and how these interacted with the expressiveness and flexibility of the visualization for exploratory analysis. As in the previous years, we also strongly encourage submissions on approaches that either did not work at all or did not live up to their expectations. We expect to get first-hand reports on lessons learned and pitfalls to be avoided.

Linux Containers have become an industry standard for sharing and distributing software. This workshop will create a space of interaction between field experts,end-users, and newcomers to discuss container technologies and their current and future challenges.

This workshop presents the current state of Linux Containers in HPC/AI, what challenges and research opportunities currently exist in the adoption in HPC/Data Analytics and how containers can foster improvements when applied to the field of HPC, Big Data and AI in the mid and long term.

The ecosystem is dissected into different layers (see below) within the workshop and presented as a curated set of lighting talks. This provides a holistic and state-of-the-art overview so that participants can make informed discussions on how to start, improve, or continue the adoption containers in HPC.

Guaranteed numerical precision of each elementary step in a complex computation has been the mainstay of traditional computing systems for many years. This era is at its twilight: to overcome the “power wall” in Exascale systems, a shift from traditional computing paradigms is now mandatory. This workshop will investigate the theoretical and practical understanding of the energy efficiency boost obtainable when accuracy requirements on data being processed, stored and communicated can be lifted for intermediate calculations. The target applications range from Big Data Analytic and Deep Learning, up to classical scientific computing simulations in HPC environments.

Topics on approximate and transprecision computing addressed in the workshop include: • Formal and mathematical methods and algorithms • Error resilient methods and algorithms • Emulation, metrics, and modeling techniques • Compiler and system software support • Emerging Technologies: hardware, processor and memory • Applications in Big Data, Analytics, Deep Learning, Scientific Computing, and HPC

After the success and great interest from the last 3 years, Arm HPC User's Group at ISC will be bringing an even more diverse and exciting panel of topics ranging from the latest Arm-based systems, to programming for arm, co-design, to new HPC areas, such as deep learning, edge, and data-center analytics.

The Arm HPC Users Group (AHUG) enables attendees to take in technical presentations by fellow applications programmers and tool authors who are currently using Arm platforms.

AHUG is about sharing experiences and knowledge. Attendees will gain from the first-hand know-how of experienced scientific application programmers writing for Arm systems, including topics such as: memory systems, scalability, vectorisation, and accelerators with Arm.

Content specifically focuses on HPC, edge computing, and everything in between. Specifically, we will include talks related to applications and cross-over/emerging application areas such as machine learning, deep learning, bioinformatics, and analytics; all on Arm-compatible platforms.

Practical compiler-enabled programming environments, applied analysis methodologies, and end-to-end toolchains can contribute significantly to performance portability in the exascale era. The practical and applied use of compilation techniques, methods, and technologies, including static analysis and transformation, are imperative to improve the performance, correctness, and scalability of high-performance applications, middleware, and reusable libraries. This workshop brings together a diverse group of researchers with a shared interest in applying compilation and source-to-source translation methodologies, among others, to enhance explicit parallel programming such as MPI, OpenMP, and hybrid models. These types of compiler technologies can also be applied to heterogeneous programming elements including FPGAs and GPUs in order to deliver higher achievable performance as compared to library-based methods and human-coded approaches taken in isolation.

Original papers will identify and solve challenges in the tradeoffs of scalability, performance, predictability, correctness, productivity, and portability on-node and at massive scale; strong-scaling, weak-scaling, and hybrid-scaling solutions assisted, augmented, and/or enabled by compiler technology are in scope. Topics of interest include but are not limited to: correctness checking of parallel programs, source-to-source translation of legacy MPI codes to improve performance-portability, instrumentation, and massively multipass FPGA compiler optimization strategies.

The Deep Learning (DL) on Supercomputers workshop provides a forum for practitioners working on any and all aspects of DL for science and engineering in the High Performance Computing (HPC) context to present their latest research results and development, deployment, and application experiences. The general theme of this workshop series is the intersection of DL and HPC; the theme of this particular workshop is the applications of DL methods in science and engineering: novel uses of DL methods, e.g., convolutional neural networks (CNN), recurrent neural networks (RNN), generative adversarial networks (GAN), and reinforcement learning (RL), in the natural sciences, social sciences, and engineering, to enhance innovative applications of DL in traditional numerical computation. Its scope encompasses application development in scientific scenarios using HPC platforms; DL methods applied to numerical simulation; fundamental algorithms, enhanced procedures, and software development methods to enable scalable training and inference; hardware changes with impact on future supercomputer design; and machine deployment, performance evaluation, and reproducibility practices for DL applications with an emphasis on scientific usage. This workshop will be centered around published papers. Submissions will be peer-reviewed, and accepted papers will be published as part of the Joint Workshop Proceedings by Springer.

High-performance computing has become central to the future success of precision medicine. Catalyzed by the dramatic increase in the volume of research and clinical data available through sequencing and advanced imaging techniques, clinical data available through medical records and mobile health devices, research data from automated platforms, combined with molecular and multi-scale simulations and the rapid adoption of deep learning approaches has created a convergence shaping the frontiers of computing and precision medicine. New approaches to drug discovery, data sharing, aggregation and safeguards, use of machine learning models in research and clinical contexts, multi-scale observations integrated with predictive modeling, and biomedical digital twins have identified new challenges and opportunities in these rapidly evolving frontiers.

The Fourth HPC Applications in Precision Medicine (HAPM) workshop will bring together the computational and life sciences communities to share experiences, examine current research and clinical data challenges, explore sharing and integration of computational approaches, data and models, and discuss opportunities to shape the future for HPC applications in precision medicine. Bringing a special emphasis for this year's workshop, the fourth HAPM workshop will highlight technologies, issues and opportunities around biomedical digital twin capabilities while continuing to highlight general and broader HPC applications of precision medicine.

Managing scientific data at scale is challenging for scientists but also for the host data center. The storage and file systems deployed within a data center are expected to meet users' requirements for data integrity and high performance across heterogeneous and concurrently running applications.

With new storage technologies and layers in the memory hierarchy, the picture is becoming murkier. To effectively manage the data load within a data center, I/O experts must understand how users expect to use these new storage technologies and what services they should provide in order to enhance user productivity. We seek to ensure a systems-level perspective is included in these discussions.

The HPC-IODC workshop addresses the storage challenge from a unique perspective, moving the focus from the application-centric perspective to the perspective of data centers and operators. In the workshop, we bring together I/O experts from data centers and application workflows to share current practices for scientific workflows, issues, and obstacles for both hardware and the software stack, and R&D to overcome these issues. We welcome submission of scientific papers with state-of-the-practice and specifically focused on I/O in the datacenter. For further information regarding participation, the topics and the mailing list, see the web page.

Imminent arrival and deployment of exascale systems among multiple hyperscaler cloud providers are expected to enable breakthroughs for various scientific disciplines. Increasingly, these systems utilize cloud technologies, enabling complex and distributed workflows that improve not only scientific productivity, but accessibility of resources to a wide range of communities. Such an integrated and seamlessly orchestrated system for supercomputing and cloud technologies is indispensable for experimental facilities that have been experiencing an unprecedented rate of data growth. While limited-scale HPC services has been available in public cloud environments, petascale and beyond data and computing capabilities are provisioned within HPC data centers using close-to-metal provisioning services to ensure performance, scaling, and cost effectiveness. This workshop aims to bring together experts and practitioners from academia, national laboratories and industry to discuss technologies, use cases and best practices in order to set a vision and direction for leveraging extreme-scale computing and on-demand cloud ecosystems.

Over the last few years, Machine Learning (and in particular Deep Learning) (ML / DL) has become an important research topic in the High Performance Computing (HPC) community. This comes along with new users and data intensive applications on HPC systems, which increasingly affects the design and operation of compute infrastructures. Bringing new users and data intensive applications on HPC systems, Learning methods are increasingly affecting the design and operation of compute infrastructures. On the other hand, the learning community is just getting started to utilize the performance of HPC, leaving many opportunities for better parallelization and scalability. The intent of this workshop is to bring together researchers and practitioners from all communities to discuss three key topics in the context of High Performance Computing and learning methods: parallelization and scaling of ML / DL algorithms, learnig applications on HPC systems, and HPC systems design and optimization for ML / DL workloads.

Workshop website: http://www.mlhpcs.org

With the hardware technology scaling and the trend on heterogeneous chip design, the existing numerical algorithms and software framework may break down due to load imbalance. There is currently a fundamental mismatch between the underlying hardware architecture with high thread concurrency and the software deployment of numerical libraries, which relies on the traditional bulk synchronous programming model. Numerical software should first squeeze performance out of single node by efficiently running on manycore architectures with processor counts sharing a common memory in the hundreds. Programming and extracting performance from these advanced architecture chips remain a challenging effort, which is further exacerbated in distributed-memory environment. Algorithmic solutions such as fine-grained computations, communication/synchronization-reducing, and mixed precisions come to the rescue. They represent some of the key ingredients to embrace for software libraries moving forward and leverage extreme-scale computing capabilities.

This half-day workshop brings together experts who lead efforts in developing innovative numerical algorithms and scalable HPC software libraries on today's architectures and upcoming Exascale systems.

Below are the main themes of the workshop: - High performance direct / iterative solvers - Mixed-precision algorithms exploiting specific hardware features - Synchronization-reducing and communication-avoiding algorithms - Performance optimizations for accelerated / hybrid architectures - Numerical libraries for large-scale scientific applications

Combination of computational fluid dynamics (CFD) with machine learning (ML) is a newly emerging research direction with the potential to enable solving so far unsolved problems in many application domains. This workshop aims to demonstrate the use of high-fidelity CFD simulations to generate data and utilize it to train ML models to better predict the underlying physics in fluid dynamics utilizing the breakthrough in computational power, the evolution of data science techniques, and the ability to generate terabytes of data from high-fidelity simulations. ML techniques have the potential to support the identification and extraction of hidden features in large-scale flow computations, hence allowing to shift the focus from time-consuming feature detection to in-depth examinations of such features. Furthermore, ML techniques have the ability to find undetected correlations between phenomena in the flow, which will lead to deeper insight of the physics involved in complex natural processes. Apart from pure fluid dynamic, other research areas, such as constitutive modeling of heterogeneous materials, multiphase flow modelling, dynamics of the atmospheric, ocean, and climate system, and combustion/chemical reactions are working on similar techniques. The workshop will stimulate this research by providing a venue to exchange new ideas and discuss challenges and opportunities.

Extreme-Scale Computing in HPC, Big Data, Deep Learning, and Clouds are marked by multiple-levels of hierarchy and heterogeneity ranging from the compute units (many-core CPUs, GPUs, APUs, etc) to storage devices (NVMe, NVMe over Fabrics etc) to the network interconnects (InfiniBand, High-Speed Ethernet, Slingshot, etc). Owing to the plethora of heterogeneous communication paths with different cost models expected to be present in extreme-scale systems, data movement is seen as the soul of different challenges for exascale computing. On the other hand, advances in networking technologies such as NoCs (like NVLink and Stormlake), emergence of new I/O interface architecture standards (CCIX, Gen-Z, CAPI etc), and RDMA enabled networks and the likes are constantly pushing the envelope of research in the field of novel communication and computing architectures for extreme-scale computing. The goal of this workshop is to bring together researchers and software/hardware designers from academia, industry and national laboratories who are involved in creating network-based computing solutions for extreme-scale architectures. The scope of the workshop includes, but not limited to: scalable communication architectures and protocols, high performance networks, runtime/middleware designs, novel hardware/software co-design, high performance communication solutions for accelerator-based computing, power-aware techniques and designs, performance evaluations, QoS, and virtualization.

The LLVM framework is a vast ecosystem surrounding a compiler core which enabled various advances in source-code tools, debuggers, linkers, and a whole host of programming-language and toolchain-related components. In addition to the open source components in the LLVM framework, e.g., Clang, Flang, MLIR, LLDB, etc., LLVM also serves as a foundation for a majority of vendor compilers and toolchains. As such, most current and future HPC system will come with LLVM components that are developed in large parts in the open source LLVM code base, a multi-company, multi-research institute, industry-academia, joint-venture.

This workshop, as its already established cousin LLVM-HPC @ Super Computing (SC), will bring together the different groups interested in LLVM: compiler and tooling developers, researchers, application specialists. The workshop features compiler and tool developers that present new features to make the community aware, researchers that discuss new ideas to gather feedback and build collaborations, as well as application specialists with experience reports and requests. As such, the workshop bridges the gap that often exists between these groups in order to generate synergies, prioritize work on practical problems, as well as amplify the usage of existing solutions.

HPC is central for empowering progress in diverse scientific and non-scientific domains. A myriad of technologies in the post peta-scale computing demand a significantly greater degree of parallelism than we currently observe. The rapid advancement of new HPC technologies has facilitated the convergence of Artificial Intelligence (AI), Big Data Analytics, and the HPC platforms to solve complex, large-scale, real-time analytics and applications for scientific and non-scientific fields. As we move towards exascale, the convergent computing platforms along with a paradigm shift in the programming applications for them provide both challenges and opportunities, for cyberinfrastructure facilitators and educators to prepare and support a diverse community of professionals to utilize evolving HPC, equipping them to solve complex scientific, engineering, and technological problems.

The HETET21 workshop is coordinated by ACM SIGHPC-Education Chapter and fosters collaborations among practitioners to explore strategies enhancing computational, data-enabled, AI and HPC educational needs. Attendees will discuss approaches for developing and deploying HPC education and training, and keeping pace with the rapid technological advances: collaborative online learning tools, technology solutions supporting HPC, Accelerated Analytics, and AI applications. The workshop will highlight: methods for conducting effective HPC education and training for emerging technologies; promote HPC educators community; disseminate best practices.

Exascale promises to support disruptive numerical experiments generating unprecedented quantity and quality of data. Only the latest advances in automated data analytics based on machine-learning or statistical analysis will make it possible to extract knowledge out of the data generated at this scale. It is thus critical to consider the numerical experiment as a whole, encompassing both its simulation (HPC) and data-analytics (HPDA) aspects. These two aspects need to be efficiently coupled to overcome the widening performance gap between compute and I/O. This also opens the road for innovative numerical patterns where the outcome of analytics is used to steer the simulation and greatly increase the scientific return of investment for numerical experiments.

HP-C/DA focuses on the latest advances and challenges for the co-execution of HPC & HPDA workloads on supercomputers. it brings together all stakeholders concerned by the in situ co-execution of HPC and HPDA workloads: 1)computer-scientists interested in high-performance applications modularization and coupling, 2)developers of services and tools for HPDA on supercomputers, 3)application developers, 4)application scientists concerned with innovative HPC & HPDA couplings at scale. The workshop will act as a discussion forum for all parties involved in order to identify the requirements and best research directions.