Reinventing HPC


Nages Sieslack: Last year’s announcement of the company’s IDM 2.0 strategy for semiconductor manufacturing represents a significant departure from Intel’s x86-only/in-house-only model. Could you talk about what drove you to switch strategies and describe exactly what this will entail?

Jeff McVeigh: Intel is dedicated to helping our customers solve the world’s greatest challenges – faster – through the superpower of high-performance computing. We need scale to achieve this, and Intel is positioned to deliver the supply of components and technologies required to fuel innovation and growth. The differentiated formula of Intel's IDM 2.0 strategy enables us to deliver a new era of innovation, manufacturing, and product leadership to our HPC customers. This includes infusing energy efficiency as we look to create more sustainable products.

IDM 2.0 enables both Intel’s HPC products and our customers to access to Intel’s advanced process technologies and the external foundry ecosystem. As the industry moves to disaggregated architectures built from multiple tiles, we’re able to deliver products that utilize the best technology for each tile and combine those with advanced packaging. This allows us to meet specific requirements across performance, energy-efficiency, supply, and cost.

Sieslack: Could you talk about some of the newer manufacturing technologies you are now employing, like SuperFIN and Foveros, and what they bring to the table?

McVeigh:  We are accelerating both our process and packaging innovations, and this is bringing immediate benefits to our upcoming supercomputing offerings.

4th Gen Intel Xeon Scalable processors will be produced on Intel 7, which is expected to deliver a 10% - 15% transistor performance-per-watt increase over Intel 10nm SuperFin, based on transistor-level optimizations. In addition, 4th Gen Intel Xeon Scalable processors will feature our EMIB packaging technology, which enables large integrations with smaller tiles at a high bump density and low latency. Using EMIB, we can build 4th Gen Intel Xeon Scalable processors on a tiled, modular SoC architecture that delivers significant scalability while still maintaining the benefits of a monolithic CPU interface.

Intel data center GPU, codenamed Ponte Vecchio is one of the most advanced products we’ve ever built. It will be Intel’s first Xe-based GPU optimized for HPC and AI workloads and features both Foveros and EMIB, which combines our advanced 3D packaging technology with 2D integration. Foveros leverages wafer-level packaging capabilities to provide a first-of-its-kind 3D stacking solution. It enables us to build processors with compute tiles stacked vertically, rather than side-by-side, for greater performance in a smaller footprint. It also lets us lay the foundation to mix and match compute tiles to optimize cost and power efficiency.

And when we launch the next generation P-core Intel Xeon processors Granite Rapids on Intel 3, it will serve as a great example of how we’re accelerating process tech for our data center products. The parallel development timeline of Intel 4 and Intel 3 has allowed our Granite Rapids team to move Granite Rapids from Intel 4 to Intel 3 with no change in the product schedule. Intel 3 will deliver an approximately 18% transistor performance improvement per watt compared to Intel 4 via enhancements like a higher performance library, optimized drive current and metal stack, and more.

Sieslack: Beyond those are the PowerVia and RibbonFET technologies that the company plans to introduce in 2024. Could you outline the significance of those advancements?

McVeigh: In the first half of 2024 we’ll be manufacturing ready with Intel 20A, which will usher in the Angstrom Era with RibbonFET and PowerVia. This will be a key moment in process technology that will deliver up to a 15% performance-per-watt improvement compared to Intel 3.

RibbonFET will be Intel’s implementation of Gate All Around (GAA) transistors, our first new transistor architecture since we pioneered FinFETs in 2011. PowerVia will be an industry-first deployment of a backside power delivery network technology when it is introduced.

By combining our torrid pace of innovation on Intel 20A with our advanced 3D packaging capabilities, we’ll be able to markedly surpass anything that we’ve previously achieved.

Sieslack: Intel recently surprised everyone with its goal to deliver zettascale capability within just five years – that is, in 2027.  What exactly are the technologies that will enable this?

McVeigh: Let’s take a step back. The demand for computing is far exceeding historical trends, driven primarily through the convergence of HPC and AI, and the opportunities these provide to help solve the world’s greatest challenges. We need to take aggressive goals now to ensure future technical solutions meet that demand. Zettascale computing is about achieving a thousand times the highest levels of today’s compute capabilities to meet the high demand for computational workloads.

Achieving such a large leap in performance requires multiple technology innovations and system-level architectural changes. We need to examine and innovate at every layer of the solution stack - silicon, software, and systems to meet the zettascale performance and the energy efficiency demands that come with it. This is the system-level thinking that is crucial to reach zettascale.

While it will require numerous innovations, we have a clear path to zettascale with this comprehensive approach that we will execute over three, multi-year phases, from ExaFLOPS in 2022 to ZettaFLOPS in 2027-2028.

  1. Exascale (2022-2023) – This phase begins next year with the introduction of products including 4th Gen Intel Xeon Scalable processors and Intel data center GPU, codenamed Ponte Vecchio, as well as our work with Argonne National Laboratory on the Aurora system. Our 2022 architectures will continue to be refined in the next generation of products.   
  2. Pre-zetta (2024-2025) – The following phase sees the introduction of products like Falcon Shores, which combines Intel Xeon and Intel Xe HPC architectures into a single package with greatly simplified programming model. It also integrates silicon photonics into chips dramatically improve the bandwidth and energy-efficiency of data movement.
  3. Zettascale (2026-2028) – This next phase will be the refinement of the many products and technologies that Intel is building over the next half-decade. We will utilize advances across architecture, process & packaging, memory, power delivery and I/O. We are working with leading technology partners to innovate and prove out these future technologies. Achieving this goal will democratize large-scale supercomputing and bring “exascale at the edge.” 

Throughout this journey, we will also continue to uphold our software-first approach to facilitate open development across the entire stack. We provide tools, platforms, and software IP to help developers be more productive and produce scalable, better-performing, and more efficient code without the technical and economic barriers of proprietary solutions.

Sieslack: With regards to your presence at ISC 2022, what can the attendees expect to see?

We’re planning an exciting program at ISC this year. I’m excited to be back in-person to host a keynote session on Tuesday, May 31 at 6:30 p.m. CEST focused on creating a sustainable and open HPC and AI ecosystem.  It is important to dramatically curtail the energy consumption and resulting climate impact driven by today’s insatiable demand for computing capacity. There is also an increasing need for democratizing compute through open standards and a reliable software stack. I’ll be joined by leading industry partners where we’ll detail silicon, software, and system-level innovations all designed to minimize “energy-to-solution” for the most demanding workloads.

My colleague Ogi Brkic, Vice President and General Manager of our AXG Super Compute Product Line will host a session on Wednesday, June 1 at 1:00 p.m. CEST on how our innovative product portfolio will provide game-changing performance and throughput to fast-track analysis and accelerate advanced scientific discoveries, from health and life sciences all the way to climate change, driving the evolution of HPC, AI and cloud visualization.  

Ogi will also be hosting a vendor showdown event on Monday May 30 at 1:00 pm CEST. Our partners in computing, networking, data and storage from Europe, Asia and North America will be joining us in a series of technical talks, fireside chats.

Last but not least, before the full conference, on Friday May 27, the oneAPI DevSummit at ISC 2022 will focus on open platforms and technologies that will advance and deploy next-generation innovations that scale across solutions from major vendors in the market.  

We'd love to have you visit the Intel booth we'll have onsite at B201. I can’t wait to see you there!

Sieslack: Thank you for your time and the invitation!

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